Method of separating a semiconductor wafer with dielectrics

ABSTRACT

A method for separating a joined substrate type wafer, which wafer is composed of a pair of semiconductor substrates joined through an insulation film, utilizes dielectrics through simple processing steps. Trenches for separating a semiconductor substrate with dielectrics are dug from the surface of the substrate and a dielectrics film is deposited on the surface of the substrate including the trenches. Then poly-crystalline silicon is grown by CVD to a thickness of about 0.5 μm, which is deep enough to fill the trenches. The process time for growing poly-crystalline silicon is shortened, and the processing step for removing the poly-crystalline silicon deposited on the unwanted areas is eliminated by growing the poly-crystalline silicon in the trenches but not on the crystalline surface of semiconductor regions based on the growth rate dependence of the poly-crystalline silicon on the crystallinity of the surface on which the poly-crystalline silicon is grown.

BACKGROUND OF THE INVENTION

The present invention relates to methods for separating a joinedsubstrate type wafer for integrated circuit apparatuses withdielectrics. More particularly, the present invention relates to amethods of separating, with dielectrics, one of the semiconductorsubstrates of a wafer joined through an insulation film into a pluralityof semiconductor regions which are insulated from each other.

Among conventional integrated circuit apparatuses, junction separationtype wafers are usually used for separating the potential of regionshousing a "built-in" semiconductor element or circuit. However, sincethe parasitic effects of known built-in transistors or diodes oftencause trouble, and mindful that involved circuits often interfere witheach other, dielectrics separation type wafers, especially the abovedescribed joined substrate type wafers, have been utilized within thecontext of integrated circuit apparatuses for high frequency use. Suchdevices are particularly suited to applications contingent upon highreliability over time.

Utilizing dielectrics separation type wafers to separate the inside ofthe integrated circuit apparatus into a plurality of mutually separatedsemiconductor regions shows that this is quite effective when done withdielectrics. Particular interest has been shown this approach amongknown devices, however, prominent difficulties remain.

The prominence of the extant difficulties among the devices of the priorart is demonstrated by reference to FIG. 3. FIG. 3 shows an example ofthe typical dielectrics separation type wafer according to the priorart. However, significant issues remain unadressed among the devices ofthe prior art. A brief perusal of conventional junction separationwafers clarifies the differences between the subject matters of thepresent invention and known apparatus.

As shown in FIG. 3, a joined substrate type wafer 10 is comprised of asemiconductor substrate 11, and an (n) type semiconductor substrate 13jointed on the substrate 11 through an insulation film 12 of siliconoxide, lapped to a predetermined thickness and mirror polished to athickness of 10 to several tens μm.

The dielectrics separation of the wafer 10 is conducted as follows.Trenches 20 are dug by etching from the surface of the semiconductorsubstrate 13 down to the insulation film 12 to divide the substrate 13to a plurality of semiconductor regions 14. The surface of each trench20 is covered with dielectrics film 30 by thermal oxidation or similarmethods which are known to those having a modicum of skill in the art.Subsequently, poly-crystalline silicon 40 is grown by a CVD method, orsimilar conventional process, so as to completely fill the trench 20with the poly-crystalline silicon 40.

The deposition of the dielectrics film 30 and the growth of thepoly-crystalline silicon 40 are conducted over the entire surface of thewafer 10. The dielectrics separation type wafer 60 of FIG. 3 iscompleted by removing the poly-crystalline silicon from the surface ofthe wafer 10. This step is undertaken to treat the entire surface ofwafer 10, except the inside of each trench 20. This step involves a dryetching technique known as etching back, and further includes removingthe dielectrics film 30 from the upper surface of the wafer 10. Thisstep excludes the surface areas around each of the trenches 20 bychemical etching using a photoresistive film as a mask.

Referring now to FIG. 4, a sectional view showing the semiconductorregions 14 of the wafer 60 separated with dielectrics is shown. In thisview, one can see that two MOS transistors are built in. Bothtransistors are separated by an element isolation film 61 which, is alocal oxidizing film (LOCOS). On the left hand side of the local oxidefilm 61, a (p) type well 71 is diffused for an n-channel transistor. Agate oxide film 72 and gates 73 are disposed for the both transistors. A(p) type source and drain layers 74, 74 and an (n) type well connectionlayer 77 are disposed for a p-channel transistor shown on the right handside, and an (n) type source and drain layers 76, 76 and a (p) type wellconnection layer 75 are disposed for an n-channel transistor shown onthe left hand side.

Usually these transistors are covered with an inter-layer insulationfilm 81, and terminals S, D and G for a source, drain and gate are ledout through windows opened in the film 81.

Longstanding problems remain to be solved by the subject matter of thepresent invention. Although the dielectrics separation type waferaccording to the prior art shows an enhanced separation performance interms of reducing the parasitic effects (or interference), productioncosts are prohibitive. Thus, each known prior art device has such anexpensive cost that none have become accepted as cost efficient enoughfor practical use.

This is because of the excessively long time involved in separating thesubstrate of the wafer with dielectrics. This is especially true inattempts to grow the poly-crystalline silicon for filling trenches inremoving the poly-crystalline silicon deposited on the unwanted areas.

Another drawback is that among conventional devices, precious areas ofthe wafer are often occupied by the separation trenches. Although thewidth of the separation trenches is generally from 5 to 15 μm, the totaloccupied area is considerably wider, since the trenches are shaped withframes or a lattice surrounding the semiconductor regions.

In order to avoid this, instead of dividing the substrate 13 for eachsemiconductor element, the substrate 13 is usually divided for eachcircuit. Each circuit is comprised of a plurality of semiconductorelements as shown in FIG. 4. However, such known separation methodstends to cause the complication that the parasitic effects cannot becompletely prevented.

In order to address these longstanding problems, the present inventionprovides a method of separating a semiconductor wafer with dielectrics.The present invention solves the problems described above which areinherent in known disclosures.

Further, prominent among the drawbacks of known dielectrics separationtype wafers are the overall production costs. The present inventionlikewise reduces the overall cost of the dielectric separationprocesses, thus enhancing the economic utility of applicants' teachings.

OBJECTS AND SUMMARY OF THE INVENTION

Accordingly it is an object of the present invention to provide a methodof separating semiconductor wafers with dielectrics which overcomes thedrawbacks of the prior art.

It is further object of the invention to provide a method of separatinga first semiconductor substrate into a plurality of semiconductorregions which are insulated from each other at a lower overallproduction cost.

Briefly stated, a method for separating a joined substrate type wafer,which wafer is composed of a pair of semiconductor substrates joinedthrough an insulation film, utilizes dielectrics through simpleprocessing steps. Trenches for separating a semiconductor substrate withdielectrics are dug from the surface of the substrate and a dielectricsfilm is deposited on the surface of the substrate including thetrenches. Then poly-crystalline silicon is grown by CVD to a thicknessof about 0.5 μm, which is deep enough to fill the trenches. The processtime for growing poly-crystalline silicon is shortened, and theprocessing step for removing the poly-crystalline silicon deposited onthe unwanted areas is eliminated by growing the poly-crystalline siliconin the trenches but not on the crystalline surface of semiconductorregions based on the growth rate dependence of the poly-crystallinesilicon on the crystallinity of the surface on which thepoly-crystalline silicon is grown.

According to an embodiment of the invention, there is provided a methodof separating a first semiconductor substrate into a plurality ofsemiconductor regions insulated from each other, the first semiconductorsubstrate constituting a jointed substrate type wafer for mounting anintegrated circuit, the wafer including said first semiconductorsubstrate joined through an insulation film with a second semiconductorsubstrate, the method comprising the steps of; digging by dry etchingnarrow trenches for separating said first semiconductor substrate withdielectrics from the surface of the first semiconductor substrate downto the insulation film, covering the surface of the wafer including thetrenches with a dielectrics film, and growing poly-crystalline siliconselectively on the dielectrics film formed on the trench faces, inamounts sufficient to fill the trenches with the poly-crystallinesilicon.

According to a further embodiment of the invention, there is provided amethod of separating a semiconductor wafer with dielectrics, said waferincluding a first semiconductor substrate joined through an insulationfilm with a second semiconductor substrate, the method comprising thesteps of; digging by dry etching narrow trenches for separating saidfirst semiconductor substrate with dielectrics from the surface of saidfirst semiconductor substrate down to said insulation film, covering thesurface of said wafer including said trenches with a dielectrics film,and growing poly-crystalline silicon selectively on said dielectricsfilm formed on the trench faces, whereby to fill said trenches with saidpoly-crystalline silicon, doping impurity selectively in the surfaces ofsaid poly-crystalline silicon grown on said trench faces, and, annealingsaid doped surfaces by thermal oxidation, for forming separation filmsabove said trenches.

The above, and other objects, features and advantages of the presentinvention will become apparent from the following description read inconjunction with the accompanying drawings, in which like referencenumerals designate the same elements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (a) is a sectional view showing the joined substrate type waferaccording to an embodiment of the method of the present invention.

FIGS. 1(b) to 1(d) are sectional views showing the steps of digging andfilling the trenches according to an embodiment of the method of thepresent invention.

FIG. 1(e) is a sectional view showing the step of impurity dopingaccording to an embodiment of the method of the present invention.

FIG. 1(f) is a sectional view showing the step of depositing theseparation film according to an embodiment of the method of the presentinvention.

FIG. 1(g) is a sectional view showing the completed dielectricsseparation type wafer according to an embodiment of the method of thepresent invention.

FIG. 2 is a sectional view expanding the main part of the wafer of FIGS.1(a) through 1(g) into which the integrated circuit is built inaccording to an embodiment of the method of the present invention.

FIG. 3 is a sectional view showing an example of the typical dielectricsseparation type wafer according to the prior art.

FIG. 4 is a sectional view expanding the main part of the wafer of FIG.3 into which an integrated circuit is built in according to the priorart typical dielectrics separation type wafer.

The present invention will be explained hereinafter with reference tothe accompanied drawing figures which illustrate the preferredembodiments of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present inventors have discovered that it is preferable to dig thetrenches by reactive ion etching method. This is the case becausereactive ion etching methods show especially strong etching anisotropy,which confines the width of the trenches within approximately 1 μm andfacilitates growth of the poly-crystalline silicon solely inside of thetrenches.

The present inventors have discovered that it is preferable to dig thetrenches by reactive ion etching method. This is the case becausereactive ion etching methods show especially strong etching anisotropy,which confines the width of the trenches within approximately 1 μm andfacilitates growth of the poly-crystalline silicon solely inside of thetrenches.

The dielectrics film is preferably composed of silicon oxide. Forgrowing the poly-crystalline silicon selectively inside the trenches, itis preferable to remove the dielectrics film from the surface areas ofthe first semiconductor substrate excluding the trenches.

Likewise, it is preferable to anneal the surface of the semiconductorregions by radiative heating in vacuum so as to improve thecrystallinity of the surface of the semiconductor regions.

Since trenches according to the present invention are narrow, it ispreferable to use the trenches for dividing the first semiconductorsubstrate into a plurality of semiconductor regions. It is likewisepreferred to build in a semiconductor element of the integrated circuitin each semiconductor region.

In other words, the area necessary for separating between thesemiconductor elements of the integrated circuit is considerably reducedby using the dielectrics separation trenches for element isolation inplace of the element separation films of the prior art. Irrespective ofwhether a semiconductor region is assigned to a semiconductor element ora plurality of elements, it is preferable to dope the impurityselectively in the surfaces of the poly-crystalline silicon grown in thetrenches and to anneal the doped surfaces by thermal oxidation so as tofacilitate the forming of separation films having greater withstandvoltage and smaller area above the trenches.

Further, according to the present invention, the step of removing thepoly-crystalline silicon from the surface of the semiconductor regionsis eliminated by utilizing the growth rate dependence of thepoly-crystalline silicon on the crystallinity of the surface on whichthe poly-crystalline silicon is deposited.

This is further done by selectively growing the poly-crystalline siliconsolely inside the trenches. Although the poly-crystalline silicon can begrown by CVD methods at high growth rates on the poly-crystallinedielectrics film which covers the trench faces. The poly-crystallinesilicon grows extremely slowly on the crystalline surface of thesemiconductor regions. While the poly-crystalline silicon grows to athickness of 0.5 μm or less, the growth of the poly-crystalline siliconon the crystalline surface of the semiconductor regions is practicallynegligible.

Based on the growth characteristics of the poly-crystalline silicon(which were just described) the separation of the semiconductorsubstrate into a plurality of regions commences by digging narrowtrenches from the surface of the first semiconductor substrate down tothe insulation film. The next step is covering the surface of the waferincluding the trenches with a dielectrics film, and growingpoly-crystalline silicon selectively on the dielectrics film formedinside faces of the trench so as to fill the trenches with thepoly-crystalline silicon.

Since the trench width is narrower than the trench width according tothe prior art, the process time for filling the trench is shortened ascompared with the prior art. Further, since the poly-crystalline silicondoes not grow on the semiconductor region, the removal process iseliminated and the process time is further shortened.

Referring now to FIG. 1(a), a wafer 10 before dielectric separation isshown. The wafer 10 is obtained by joining an (n) type semiconductorsubstrate 13 with resistivity of 10 to 20 Ω cm at 1000 degrees C. withan appropriate semiconductor substrate 11.

This is done through an insulation film 12 of 1 μm in thickness made ofsilicon oxide, by lapping the substrate 13 to a desired thickness ofaround 10 μm and by mirror polishing the surface of the substrate 13.

Referring now to FIG. 1(b) the wafer 10 is shown after trenches havebeen dug. In digging the trenches, the substrate 13 is divided into aplurality of semiconductor regions 14 by digging trenches 20 deep downto the insulation film 12 in a narrow width by a dry etching method.

In preparation for this step, it is preferable to initially cover thesurface of the wafer 10 with a thin oxide film for contaminationprevention. This film should have a thickness of approximately 0.05 μmand be created by thermal oxidation, and to implant B₁₁ under anacceleration voltage of 80 keV and at a dosage amount of 1.2×10¹³atoms/cm².

It is then preferable to spin coat a photoresistive film on the oxidefilm, open windows shaped with the trench pattern through thephotoresistive film, and then, remove the oxide film in the windows bydry etching. It is preferable to utilize a reactive ion etching method,which uses SF₆ as the etching gas and is highly advantageous foranisotropic etching. This is also important for accurately digging thenarrow trenches 20 deeply using the photoresistive film as the maskingelement.

According to the present invention, since it is preferable to dig eachof the trenches 20 within a width of about 1 μm, or less [following thestep of insulating the trenches which is explained in detail in FIG.1(c)], it is preferable to set the width of the windows opened throughthe photoresistive film at 1 to 1.5 μm.

From FIG. 1(b) on, the width of the windows is exaggerated in comparisonwith their depth for the sake of clear illustration. After the trenches20 have been dug, the photoresistive film is removed initially, and thenthe thin oxide film is removed with dilute hydrofluoric acid from thesurfaces of the semiconductor regions 14 as shown in FIG. 1(b).

Referring now to FIG. 1(c) trenches 20 are shown as already insulated.In the step of insulating the trenches, the entire surface of the wafer10 including the inside faces of each of the trenches 20 and the surfaceof the semiconductor regions 14 are covered with a dielectrics film 30.Conventional silicon oxide films may be used as the dielectrics film 30.Such silicon oxide film thickness is preferably set at about 0.3 μm,corresponding to the withstand voltage necessary between thesemiconductor regions 14, 14.

To obtain a dielectrics film 30 having an improved and enhanced filmquality, the oxide film is formed by a pyrogenic method. Such apyrogenic method uses H₂ and O₂, under atmospheric pressure at fromabout 800 to 850 degrees C. for 3 hrs.

Referring now to FIG. 1(d), the wafer 10 is shown in a state in whicheach of the trenches 20 have been filled. According to the method of thepresent invention, during a filling step, each of the trenches 20 arefilled with poly-crystalline silicon 40 grown selectively on thedielectrics film 30. During this step, it is preferable to expose thecrystalline surface of the semiconductor regions 14 in advance so as togrow the poly-crystalline silicon 40 solely inside the trenches 20 butso as not to grow the poly-crystalline silicon 40 on the other parts ofthe wafer 10.

In order to expose the crystalline surface of the semiconductor regions14, the dielectrics film 30 on the semiconductor regions is exclusivelyetched and removed a reactive ion etching method. This is preferablydone under a reduced pressure of 1 to several mTorr in a mixed gasenvironment containing C₂ ClF₅ and O₂, and then the disorder of thesurface crystallinity is annealed out by heating at approximately 1000degrees C. in vacuum for 2 min. with a lamp.

The poly-crystalline silicon 40 is grown by the CVD method using asilane reaction gas under reduced pressure of 0.3 Torr at 620 degrees C.A growth time is set at about 2 hrs so as to maintain a film thicknessof around 0.5 μm or less. Under the growth conditions described above,the poly-crystalline silicon 40 does not grow on the surface of thesemiconductor regions 14, especially not on the crystalline surface. Thepoly-crystalline silicon 40 grows solely from the dielectrics film 30,and in each of the trenches 20 and completely fills the trenches 20 fromboth sides as shown in the figure.

Referring now to FIG. 1(e), a preparatory impurity doping step for thegrowth of the separation film 50 is shown. In this step, (n) or (p) typeimpurity I is doped by ion-implantation in the poly-crystalline silicon40. As a preparatory step for the ion implantation, a thin oxide film isdeposited in the state of FIG. 1(d) on the entire surface of the wafer10 to a thickness of 0.02 μm, a photoresistive film for the masking M ofFIG. 1(e) is coated to a thickness of around 0.7 μm, windows are openedcorresponding to each of the trenches 20, and the oxide film is removedfrom above the poly-crystalline silicon 40 by etching back in O₂ or in agas mixture of CF₄ and O₂.

As₇₅ is preferable for impurity I. The surface area of thepoly-crystalline silicon 40 is heavily doped with As₇₅ by shallowimplantation of As₇₅ at an acceleration voltage of 70 keV and at a doseamount of 3×10¹⁵ atoms/cm².

An (n) type impurity P₃₁ or a (p) type impurity B₁₁ may be used as theimpurity I per the requirements of the individual application. Afterdoping the impurity I, the masking M is removed by ashing, and the oxidefilm by etching back.

Referring now to FIG. 1(f), although the separation of the wafer 10 withdielectrics is substantially completed through the steps described sofar, a separation film 50 of silicon oxide is formed over each of thetrenches 20. During the separation film deposition process of FIG. 1(f),the surfaces of the poly-crystalline silicon 40 and the semiconductorregions 14 are oxidized by the pyrogenic oxidation method at 800 degreesC. for about 2 hrs. The oxide film is deposited in this step to athickness of 0.3 ×m as the separation film 50 on the poly-crystallinesilicon 40 doped with the impurity I, but to an extremely thin thicknessof 0.05 ×m as designated by reference numeral 51 on the semiconductorregion 14.

Referring now to FIG. 1(g), a completed wafer 10 is shown as adielectrics separation type wafer 60. To bring the wafer 10 to thiscompleted state, the very thin oxide film 51 is removed from the surfaceof the semiconductor regions 14 with hydrofluoric acid, leaving theseparation film 50 unremoved.

However, when MOS transistors are built in the wafer 60, it ispreferable to regulate the surface impurity concentration of thesemiconductor region in advance to the removal of the oxide film 51 byshallowly implanting ions at a dose amount of 2.8×10¹² atoms/cm² fromBF₂ under an acceleration voltage of 65 eV.

Referring now to FIG. 2, the wafer 60 is separated with dielectrics inwhich MOS transistors are built in. In the embodiment shown in the FIG.2, a p-channel MOSFET is built in a semiconductor region 14 on the righthand side of the figure and an n-channel MOSFET on the left hand side.The processes for building in these elements is further detailed in thediscussion directly below.

Initially, a (p) type well 71 is diffused to a depth of about 4 μm inthe left hand side region 14 in which the n-channel MOSFET is to bebuilt in. Then a gate oxide film 72 is deposited to a thickness of 0.025μm, phosphorus doped poly-crystalline silicon is grown for gates 73, 73to a thickness of 0.3 μm, and the poly-crystalline silicon is annealedat 900 degrees C. for 20 min.

The annealed poly-crystalline silicon is shaped with the gates 73, 73 byphoto-etching, and the damages caused by the etching are removed byannealing the shaped poly-crystalline silicon in an N₂ gas at about 900degrees C. for 10 min.

Preferably, the gates are oxidized to form on the lower side edges oftheir respective end faces a shadow oxide film to a thickness of about0.02 μm to improve the withstand voltage.

Then, source and drain layers 74, 74 and a substrate connection layer 77of the p-channel transistor, and source and drain layers 76, 76 and asubstrate connection layer 75 of the n-channel transistor are formed byimplanting (n) type and (p) type impurities through the photoresistivemasking. An oxide film of approximately 0.12 μm in thickness and aborophosphosilicate glass film of 0.65 μm are deposited by a CVD methodat 800 degrees C. to form an inter-layer insulation film 81.

A titanium film of about 0.02 μm in thickness, titanium nitride film ofabout 0.1 μm in thickness and an aluminum film of about 0.5 μmcontaining 1% of Si and 0.3% of Cu are deposited to form a wiring film82 and the wiring film 82 is patterned to form terminals of a source S,drain D and gate D. Thus, the MOSFETs are built in as illustrated inFIG. 2.

In the integrated circuit of FIG. 2 built into the dielectricsseparation type wafer 60 according to the present invention, the widthof each of the trenches 20 for the dielectrics separation is narrowed toless than a quarter of the width of the conventional integrated circuitof FIG. 4. Therefore, the necessary area for building in the integratedcircuit is narrowed. By separating the semiconductor regions 14 at everysemiconductor element, the aforementioned parasitic effect andinterference between the circuit are practically completely prevented.Besides, the area necessary for separating the semiconductor elementsfrom each other is more narrowed than that for the element separationfilm 61 of FIG. 4, and some steps for forming the element separationfilm 61 are eliminated.

Usually, the element separation film 61 is built in by a known,selective oxidation method, which requires the deposition and patterningof the nitride masking film, impurity diffusion for the channel stopper,the high temperature thermal oxidation of the element separation filmand removal of the nitride film by dry etching. In contrast, the presentinvention facilitates separating simultaneously the wafer 60 withdielectrics and the elements from each other.

Though not shown in FIG. 2, the wiring film 82 is usually covered with aprotection film. An oxide film about 0.1 μm in thickness, phosphorussilicate glass about 0.3 μm in thickness and silicon nitride film about1 μm in thickness are formed, and windows are opened through the filmlamination composite for the terminals of the connection pads etc. inthe predetermined positions of the composite. Though the constituentelement of the integrated circuit is explained by way of a MOStransistor, the constituent element such as a DMOS transistor, bipolartransistor, insulated gate bipolar transistor, etc. may be built in thewafer 60 separated with dielectrics.

Since the dielectrics separation type wafer is well suited for the MOStransistors with the so-called LDD (lightly doped drain) structure, themanufacturing process for the transistor will be briefly explainedbelow. At first, the joined substrate type wafer 10, the substrate 13 ofwhich has an appropriate thickness is processed to the dielectricsseparation type wafer 60 through the above described steps. After thegates 73, 73 are disposed, the (n) type impurity such as P31 isimplanted under the acceleration voltage of 30 keV at the dose amount of3×10₁₃ atoms/cm² using a photoresistive film for forming the source anddrain layers 76, 76 as the masking. After removing the photoresistivefilm, an oxide film is formed to a predetermined thickness by CVD at 800degrees C.

The oxide film is removed by etching back leaving space oxide films by awidth of around 0.2 μm on the side walls of the gate 73. Then the (n)type impurity is implanted for forming the source and drain using thespace oxide films as a part of the masking. The successive steps are thesame as those of FIG. 2.

The present invention is further characterized by the above describedspecific features, and additionally shows the following favorableeffects:

i. since it is enough to grow the poly-crystalline silicon so as to fillthe narrow trench, the process time for filling the trenches isshortened to less than a quarter of the process time by the prior art;

ii. since the poly-crystalline silicon never grows on the areas otherthan the trenches, the step of removing the excessive poly-crystallinesilicon is eliminated, and the cost of separating the wafer withdielectrics is greatly reduced.

Likewise, the following subsidiary effects are obtained by the presentinvention:

i. since the area necessary for separating the wafer with dielectrics isreduced, the chip size of the integrated circuit apparatuses is alsoreduced;

ii. since the amount of the poly-crystalline silicon for filling thetrenches is reduced to less than a quarter of the amount by the priorart, bending of the wafer, often caused by the high temperature processof building in the integrated circuit, is eliminated.

The selectivity of the growth of the poly-crystalline silicon to thetrenches is improved and the above described effects are enhanced bydigging the trenches within the width of about μm, removing thedielectrics film from the surface areas on the semiconductor regionsexcept the trenches and annealing the thus exposed surfaces by radiativeheating in vacuum.

The chip size of the integrated circuit apparatuses is reduced throughthe reduction of separation area between the elements even when thewafer is divided by the trenches into the semiconductor regions, in eachof which one semiconductor element is built in. The withstand voltagebetween the semiconductor regions and the performance of the integratedcircuit apparatuses are improved by forming the separation film ofsilicon oxide through the selective impurity doping in the surface layerof the poly-crystalline silicon in the trenches. And, the manufacturingcost of the integrated circuit apparatuses is reduced by simultaneouslyconducting the dielectrics separation and the separation between thesemiconductor elements.

In summary, the present invention utilizes the growth rate dependence ofthe poly-crystalline silicon on the crystallinity of the surface onwhich the poly-crystalline silicon is deposited by the CVD method. Inseparating the joined substrate type wafer with dielectrics, narrowtrenches are dug deeply down to the insulation film from the wafersurface by dry etching, the wafer surface including the inside faces ofthe trenches is covered with a dielectrics film, and thepoly-crystalline silicon is selectively grown by CVD solely on thedielectrics film on the inside faces of the trenches.

Having described preferred embodiments of the invention with referenceto the accompanying drawings, it is to be understood that the inventionis not limited to those precise embodiments, and that various changesand modifications may be effected therein by one skilled in the artwithout departing from the scope or spirit of the invention as definedin the appended claims.

What is claimed is:
 1. A method of separating a first semiconductorsubstrate into a plurality of semiconductor regions insulated from eachother, said first semiconductor substrate constituting a jointedsubstrate type wafer for mounting an integrated circuit, said waferincluding said first semiconductor substrate joined through aninsulation film with a second semiconductor substrate, the methodcomprising the steps of:dry etching trenches, for separating said firstsemiconductor substrate with dielectrics, from a surface of said firstsemiconductor substrate down to said insulation film; covering saidsurface including said trenches with a dielectrics film; removing saiddielectrics film from said surface, excluding said trenches; and growingpoly-crystalline silicon selectively on said dielectrics film remainingon faces of said trenches, thereby filling said trenches with saidpoly-crystalline silicon.
 2. The method as claimed in claim 1, whereinsaid step of digging further includes said trenches being confined to awidth of about 1 μm.
 3. The method as claimed in claim 1, wherein saidstep of covering includes said dielectrics film further comprisingsilicon oxide.
 4. The method as claimed in claim 1, wherein said step ofremoving includes reactive ion etching.
 5. The method as claimed inclaim 1, further including annealing said surface by radiative heatingin vacuum following said step of removing said dielectrics film fromsaid surface.
 6. The method as claimed in claim 1, wherein said firstsemiconductor substrate is divided into a plurality of semiconductorregions, wherein each of said plurality of semiconductor regions has asemiconductor element of said integrated circuit built in.
 7. The methodas claimed in claim 1, further comprising the steps of:doping impurityselectively in the surfaces of said poly-crystalline silicon grown onsaid trench faces; and, annealing said doped surfaces by thermaloxidation, for forming separation films above said trenches.
 8. Themethod as claimed in claim 2, further comprising the steps of:dopingimpurity selectively in the surfaces of said poly-crystalline silicongrown on said trench faces; and, annealing said doped surfaces bythermal oxidation, for forming separation films above said trenches. 9.The method as claimed in claim 3, further comprising the steps of:dopingimpurity selectively in the surfaces of said poly-crystalline silicongrown on said trench faces; and, annealing said doped surfaces bythermal oxidation, for forming separation films above said trenches. 10.The method as claimed in claim 4, further comprising the steps of:dopingimpurity selectively in the surfaces of said poly-crystalline silicongrown on said trench faces; and, annealing said doped surfaces bythermal oxidation, for forming separation films above said trenches. 11.The method as claimed in claim 5, further comprising the steps of:dopingimpurity selectively in the surfaces of said poly-crystalline silicongrown on said trench faces; and, annealing said doped surfaces bythermal oxidation, for forming separation films above said trenches. 12.The method as claimed in claim 6, further comprising the steps of:dopingimpurity selectively in the surfaces of said poly-crystalline silicongrown on said trench faces; and, annealing said doped surfaces bythermal oxidation, for forming separation films above said trenches. 13.A method of separating a semiconductor wafer with dielectrics, saidwafer including a first semiconductor substrate joined through aninsulation film with a second semiconductor substrate, the methodcomprising the steps of:dry etching trenches, for separating said firstsemiconductor substrate with dielectrics, from a surface of said firstsemiconductor substrate down to said insulation film; covering saidsurface, including said trenches, with a dielectrics film; removing saiddielectrics film from the surface of said wafer, excluding saidtrenches; and growing poly-crystalline silicon selectively on saiddielectrics film formed on faces of said trenches, thereby filling saidtrenches with said poly-crystalline silicon; doping impurity selectivelyin surfaces of said poly-crystalline silicon grown on said trench faces;annealing said surfaces of said poly-crystalline silicon; and formingseparation films above said trenches by thermal oxidation.